This invention relates to integrated circuits such as programmable logic device integrated circuits, and more particularly, to circuitry that compresses parallel data into a more serialized format to reduce the overhead associated with providing large numbers of parallel interconnect lines when conveying data across a chip.
Integrated circuits such as programmable logic devices typically contain logic resources whose operation can be programmed using configuration data. A user can customize a programmable logic device to perform a desired logic function by loading appropriate configuration data into the device. The programmable resources on a programmable logic device can be used to implement memory and digital signal processing functions. However, using general-purpose programmable resources to implement complex memory or digital signal processing circuits can be inefficient. As an example, implementing an 18-bit×18-bit multiplier using general-purpose programmable logic resources may consume ten times more circuit real estate than implementing the same type of multiplier using a dedicated multiplier circuit.
As integrated circuit dimensions shrink due to advances in process technology, the sizes of the transistors on a circuit often scale more rapidly than the sizes of the interconnect conductors used to transport signals between different locations on the circuit. This trend makes it increasingly important to minimize the amount of circuit resources used for forming interconnects.
Dedicated circuits such as digital signal processing circuits and memory often have large numbers of associated inputs and outputs. For example, a true dual-port 18-bit memory has 36 input data lines and 36 output data lines. An 18 bit multiplier has 36 data input lines and 36 data output lines. Additional lines are needed for clock signals and control signals.
When large groups of interconnect lines such as the interconnect lines traditionally associated with memory and signal processing circuit blocks extend across a significant portion of an integrated circuit, a correspondingly large portion of the interconnect resources of the integrated circuit are consumed and are therefore not available to support other signal routing tasks.
It would be desirable to be able to provide ways in which to minimize interconnect resource consumption on integrated circuits such as programmable logic devices.